1. Field of the Invention
The present invention relates to the field of successive approximation analog-to-digital converters.
2. Prior Art
A traditional successive approximation (SAR) analog-to-digital converter (ADC) is schematically shown in FIG. 1. The specific converter shown uses a differential switched capacitor DAC coupled to a comparator having an output coupled to a successive approximation register controlling non-overlapping switch drivers coupled to the switched capacitor DAC. An analog input sample-and-hold is provided, which may be the switched capacitor DAC itself, with the overall SAR ADC being controlled by some form of controller such as the state machine shown.
In a switched capacitor DAC, the capacitor values may be in a binary sequence (radix=2) with one terminal of all capacitors connected to the DAC output. (Reduced radix and mixed radix DACs are also known, to which the present invention is equally applicable.) In a differential switched capacitor DAC as shown, two single-ended DACs operate in opposite polarity so that the outputs of the two DACs may be compared by the comparator, rather than a single output compared to ground as in a single-ended DAC. In operation, the DAC output is switched to ground and the capacitors are all simultaneously connected to and charged to the analog input voltage in the analog input sample-and-hold circuit. Then the grounding is removed and each capacitor is coupled to a reference voltage, one at a time, starting from the most significant bit (the largest capacitor). Typically the capacitance representing the least significant bit is replicated so that the capacitance of the most significant bit is equal to the sum of all of the rest of the capacitances. Thus when the switch drivers connect the capacitance associated with the most significant bit to the reference voltage, the comparator will reverse state if the analog input voltage was less than half the reference voltage, but will not reverse state if it is more than half of the reference voltage VREF. If the comparator does reverse state, than the non-overlapping switch driver associated with the most significant bit is reset (the capacitor reconnected to the analog input signal), otherwise it is left set. Either way, the comparator output will remain, or return, respectively, to its original state. Then the next overlapping switch driver is set, and left set if the output of the converter does not change, or reset if the output of the comparator does change, again after which the comparator will remain or return to its original state again. The sequence is repeated until the least significant bit is tested, after which the latches in the successive approximation register controlling the non-overlapping switch drivers will contain the digital value of the analog input signal held in the analog input sample-and-hold. A more complete description of the operation of a switched capacitor DAC analog-to-digital converters may be found in “Bipolar and MOS Analog Integrated Circuit Design” by Alan B. Grebene, a Wiley-Interscience Publication, 1984, starting on page 853.
In such analog-to-digital converters, non-overlapping switch drivers are required to control the switches in the switched capacitor DAC for proper operation of the algorithm. The speed of a successive approximation ADC is normally limited by the sum of the delays through the comparator, the successive approximation register, the non-overlapping drivers and switched capacitor DAC. Such delays can be substantial given the fact that the sequence must be repeated in a non-overlapping fashion for each successive bit in each multiple bit conversion. Additional delays are introduced when level shifters are needed, as when the digital and analog portions of the circuit are driven from separate supply voltages. In that regard, level-shifting is often used because high analog supply voltages are desirable for performance reasons, but small-geometry digital CMOS gates often can't tolerate those larger voltages. Thus, it's often necessary to use larger geometry devices in the analog supply section and add level-shifting at some point between analog and digital sections. Without level-shifting, a high input from the low-voltage section will not be high enough to completely turn off the PMOS devices, allowing static supply current to flow, potentially giving incorrect CMOS logic levels.
FIG. 2 provides an example of a prior art implementation of a successive approximation register 20 and non-overlapping switch drivers 22 as separate functions. Each latch must set before the respective switch driver is initiated, and if the comparator output (FIG. 1) changes state, must reset before the switch drivers are themselves reset.
FIG. 3 provides an example of a prior art implementation of a supply voltage level shift and non-overlapping switch driver as separate functions. The supply voltage level shift is provided by flip-flop circuit 24 powered by typically a higher voltage supply and controlled by lower voltage inputs INPUT and {overscore (INPUT)}, which may be the Q and {overscore (Q)} outputs of successive approximation latches as shown in FIG. 2. The high voltage referenced output of the flip-flop circuit is coupled to the non-overlapping switch drivers 26, also powered from the higher voltage supply.
The feedback connections in the level-shifter of FIG. 3 perform the level-shift as follows. When NMOS transistor Q2 is turned off and NMOS transistor Q1 is turned on, the gate of feedback PMOS transistor Q6 is pulled low, causing the gate of the PMOS transistor Q5 to be pulled all the way to the high supply voltage, completely turning off PMOS transistor Q5. Of course, when NMOS transistor Q1 is turned off and NMOS transistor Q2 is turned on, the opposite sequence happens. The transistors must be sized so that the NMOS devices are strong enough to pull the output low initially until the feedback comes back and fully turns off the PMOS transistors Q5 or Q6.